1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a flash memory device having a stable source line, irrespective of bit line coupling during a read operation and irrespective of loading effect experienced during a manufacturing process.
2. Discussion of the Related Art
Flash memory devices are widely deployed in computers and electronic communication systems that require a storage function. In flash memory devices, non-volatility and on-chip programmability are important factors for storing data in various applications. For example, flash memory devices are used to store BIOS startup information for a personal computer or to store programs or data files for portable equipment such as mobile telephones and digital cameras.
Unlike volatile memory devices such as dynamic random access memory (DRAM), the flash memory device performs erase and program operations. FIG. 1 is a cross-sectional view of a split-gate NOR flash memory device, and FIG. 2 is a schematic illustration of the flash memory cell which is an equivalent circuit of the split-gate NOR flash memory device of FIG. 1. Referring to FIG. 1, the split-gate NOR flash memory device 100 includes a source region 102 and a drain region 103 formed on a semiconductor substrate 101 and spaced apart from each other by the length of a channel region 104, a floating gate 105 formed over predetermined portions of the source region 102 and the channel region 104, and a control gate 106 formed over both the floating gate and the channel region 104 disposed at a lateral portion of the floating gate 105. The split-gate NOR flash memory device 100 performs a program operation by accumulating negative charge in the floating gate 105, and performs an erase operation by tunneling the accumulated charge to the control gate 106 at a peaked portion A of the floating gate 105.
In the schematic representation of the flash memory cell 200 of FIG. 2, a memory transistor 201 and a selection transistor 202 are serially connected between a source line SL and a bit line BL and gated to a word line WL. The program or erase operation of the flash memory cell 200 is achieved under the conditions of TABLE 1.
TABLE 1OPERATINGSELECT/MODEUNSELECTEDBLWLSLBULKPROGRAMSELECTED0 VVTVpp0 V(1.5 V)(10 V)MODEUNSELECTEDVCC0 V0 V0 VERASESELECTED0 VVee0 V0 V(12 V)MODEUNSELECTED0 V0 V0 V0 VREADSELECTED1 VVread0 V0 V(3 V)MODEUNSELECTED0 V0 V0 V0 V
In TABLE 1, when applying 0 V to the bit line BL, 1.5 V (threshold voltage of transistor) to the word line WL, 10 V (high voltage Vpp) to the source line SL and a bulk voltage of 0 V, charge is accumulated in the floating gate 105 of the memory transistor 201 to thereby achieve the program operation of the flash memory cell 200. If applying 0 V to the bit line BL, 12 V (erase voltage Vee) to the word line WL, 0 V to the source line SL and a bulk voltage of 0 V, the accumulated charge of the floating gate 105 is discharged to thereby achieve the erase operation of the flash memory cell 200. The read operation of the flash memory cell 200 is achieved by applying 1 V to the bit line BL, 3 V (read voltage Vread) to the word line WL, 0 V to the source line SL and a bulk voltage of 0 V. At this time, if a selected memory cell is a programmed cell, current does not flow between the drain and the source of the memory transistor 201, and thus, the memory cell is referred to as being “off”. Meanwhile, if a selected cell is an erased cell, constant current flows between the drain and the source of the memory transistor 201, and thus, the memory cell is referred to as being “on”.
Memory cell array blocks 300 and 400 consisting of these memory cells are shown in FIGS. 3 and 4. FIG. 3 is a view of a conventional memory cell array block 300 in which a plurality of bit lines are connected with one I/O line. Referring to FIG. 3, the memory cell array block 300 includes n×m memory cells Q1 to Q16 connected with n word lines WL and m bit lines BL, selection transistors QS1 to QS4 connected with n/2 source lines SL1 to SLn/2, column selection transistors NM1 to NM6 connected with column addresses YA1, YAi, YB1 and YBj, a discharge transistor NM7 connected with a source line discharge signal SL_DIS, and a source line decoder 310. For example, the memory cells Q1 to Q8 and the selection transistors QS1 and QS2, which are connected with the first and second word lines WL1 and WL2, are connected with the first source line SL1, thereby forming one page unit PAGE1. Hence, the memory cell array block 300 is constituted with n/2 pages and each page is a basic unit of an erase mode. The source line decoder 310, which will be described below, controls the application of 0 V or VPP voltage to the source lines SL1 to SLn/2 according to the mode of operation. Data of the selected memory cells Q1 to Q16 are connected with a sense amplifier S/A via the column selection transistors NM1 to NM6 and transmitted to the I/O line.
Recently, meanwhile, micro controllers with built-in nonvolatile memory (NVM) or smart cards with built-in CPU capability tend to require memory devices with ever-increasing capacity. While a conventional EEPROM provided with memory cells consisting of two transistors offers the advantage that the program and erase operations can be performed based on byte and page units, it also has the disadvantage that the cell size is comparably large. While an EPROM offers the advantage that the cell size is small, it has a disadvantage that it cannot be used as a data memory device since it cannot be erased while mounted to a circuit board. Particularly, for a smart card application, where there is a demand for large-capacity program memory and data memory capable of performing the program and erase operations, whether in units of bytes or pages, the flash memory devices are employed. Although flash memory devices suffer from problems such as increased layout area consumption when the program and erase operations are performed using the byte mode, these problems can be solved by reducing the page unit using small bytes. FIG. 4 illustrates a memory cell array block 400 having a plurality of I/O lines I/O1 to I/Ok, in which the page unit size is reduced. Respective bit lines BL1 to BLk are connected with sense amplifiers S/A1 to S/Ak via transistors NM1 to NM4 gated to a column selection signal YSEL and are connected with I/O lines I/O1 to I/Ok.
The memory cell array blocks 300 and 400 operate as shown in TABLE 1. For example, during a read operation, when the source lines SL1 to SLn/2 (on the whole, referred to as “SLi”) are set to a ground voltage (VSS), cell currents of the selected memory cells can flow. The sense amplifiers S/A sense and amplify the cell currents and transmit memory cell data to the I/O lines I/Ok. Meanwhile, during the read operation, if “on” cells exist adjacent to “off” cells, the voltage levels of the bit lines corresponding to the “on” cells will become reduced, due to the cell currents, and voltage levels of the bit lines corresponding to the “off” cells are also reduced due to coupling between adjacent bit lines, causing the problem that the cell currents can flow through the “off” cells like they do through the “on” cells. This phenomenon causes a read failure. Even if discharge path within the source decoder 310 is large, potentials of the source lines SLi do not fully become the ground voltage (VSS), but rather rise to some extent due to junction diffusion resistance and line resistance, which are caused by an arrangement of the source lines SLi. In this case, the potentials of the source lines SLi can be made to go down by forming additional discharge paths on the source lines SLi or by using a metal strapping method.
However, the method of forming additional discharge paths carries with it the disadvantage that the chip may increase in size. Also, the method of forming metal strapping or transistors between the memory cell array and with a different shape from the memory cell patterns is limited by resulting degradation of the characteristics of the memory cells due to loading effect which occurs in the memory cells during manufacturing processes.
Therefore, there is an increased demand for memory cells capable of solving the rising voltage problem of the source lines, without increasing the size thereof and without worsening the loading effect of the memory cells.